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Listed two days ago

IC Design Engineers – Multiple Roles

at Silicon Quantum Computing

This is a Full time job

Sydney NSW
Design breakthrough cryo‑CMOS chips that power quantum computers, pushing hardware beyond classical limits and enabling real quantum advantage.
Design breakthrough cryo‑CMOS chips that power quantum computers, pushing hardware beyond classical limits and enabling real quantum advantage.
subClassification: Electrical/Electronic EngineeringElectrical/Electronic Engineering
classification: Engineering(Engineering)
2d ago
2d ago
Listed fifteen days ago

Software Engineer (Operational Systems)

at Deep C Holdings PTY LTD

This is a Full time job

Sydney NSW(Hybrid)
$90,000 – $120,000 per year
Full-stack engineer for China-facing systems and semiconductor workflow tooling. Mandarin fluency and EDA experience required. Sydney-based.
Full-stack engineer for China-facing systems and semiconductor workflow tooling. Mandarin fluency and EDA experience required. Sydney-based.
subClassification: Engineering - SoftwareEngineering - Software
classification: Information & Communication Technology(Information & Communication Technology)
15d ago
15d ago
Listed twenty three days ago

FPGA Engineer

at Skykraft

This is a Full time job

Canberra ACT
Ready to build FPGA solutions that operate in space? Apply now and help us deliver next‑generation air traffic services from orbit.
Ready to build FPGA solutions that operate in space? Apply now and help us deliver next‑generation air traffic services from orbit.
subClassification: Aerospace EngineeringAerospace Engineering
classification: Engineering(Engineering)
23d ago•Expiring
23d ago•Expiring
Listed seventeen days ago

AI Model Engineer

at Cadence Connect

This is a Full time job

Brisbane QLD(Hybrid)
  • Own and improve generative models producing Verilog/SystemVerilog RTL
  • Build agentic workflows Engineers can actually trust!
  • Exclusive retained search via Cadence Connect - travel required.
  • Own and improve generative models producing Verilog/SystemVerilog RTL
  • Build agentic workflows Engineers can actually trust!
  • Exclusive retained search via Cadence Connect - travel required.
If you're a technically astute ML Engineer who likes being tested, measured and stretched...this will interest you.
If you're a technically astute ML Engineer who likes being tested, measured and stretched...this will interest you.
Recruited byMike Priest
subClassification: Engineering - SoftwareEngineering - Software
classification: Information & Communication Technology(Information & Communication Technology)
17d ago
17d ago
Listed sixteen hours ago

FPGA Design Engineer, Sydney

at Arista Networks
Be an early applicant

This is a Full time job

Sydney NSW
We are seeking skilled and motivated individuals to join our FPGA development team. The successful candidate will be responsible for the design,...
We are seeking skilled and motivated individuals to join our FPGA development team. The successful candidate will be responsible for the design,...
subClassification: Electrical/Electronic EngineeringElectrical/Electronic Engineering
classification: Engineering(Engineering)
16h ago
16h ago
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